Rendering of Higher-Order Trimmed Rational Tensor-Product Bezier-Patches Using Hardware Tessellation

Bachelor-Thesis

In CAD models are represented by trimmed tensor-product patches. The degree of these surfaces ranges usually from 1 x 1 up to 10 x 10 and higher.

Recently, tessellation capabilities have been made available on graphics hardware. However, the hardware only supports patches having at most 32 control points. The goal of the thesis is to implement a framework that uses the tessellation hardware of modern graphics hardware and that is able to render large sets of trimmed (rational) tensor-product Bézier-patches in real-time using Direct3D 11 tessellation hardware.
Requirements: A prospective candidate should have attended classes and exercises in Computer Graphics. Having attended "GRAPA" is a plus. Direct3D 11 expertise can be acquired throughout the course of the thesis.

Advisor(s)